1. Technical Field
Embodiments of the invention relate to semiconductor devices, and, in particular, semiconductor devices that include a surge protection element, such as an ESD protection element.
2. Related Art
Several features generally demanded of semiconductor devices used in automobiles include, for example, a low on-state resistance, high withstand, and low cost. Together with a low on-state resistance, a high surge withstand is demanded of the semiconductor devices used in the load drive of an automobile lamp, relay, or the like, as electromagnetic noise from a surge voltage caused by electrostatic discharge (ESD), an induction load (L load), or the like, is applied from an output terminal thereof.
Also, in an integrated circuit, in order to prevent an excessive current flowing through an internal circuit configuring the integrated circuit, and the internal circuit being destroyed, when a surge (for example, an ESD surge) is applied from an input terminal or output terminal, a surge protection element such as an ESD protection element is formed on the same chip as the internal circuit.
FIG. 7 is a main portion plan view of a conventional semiconductor device 500. FIGS. 8A and 8B are enlarged views of a B portion of FIG. 7, wherein FIG. 8A is a main portion plan view of an output stage MOSFET 501, and FIG. 8B is a main portion sectional view taken along an X-X line of FIG. 8A. FIG. 9 is a main portion plan view of electrode wiring of the semiconductor device 500 of FIG. 7.
In FIGS. 7 to 9, the semiconductor device 500 includes an n-type well region 52 disposed in a surface layer of a p-type semiconductor substrate 51, a plurality of (lateral n-type MOSFET) stripe-form p-type well regions 54 disposed in the n-type well region 52 and configuring a cell of an output stage MOSFET 501, stripe-form n-type source regions 56 disposed in a surface layer of the p-type well region 54, and a stripe-form p-type contact region 57 disposed sandwiched by the n-type source regions 56. The semiconductor device 500 includes a gate electrode 61, formed of polysilicon, disposed across a gate oxide film 41 on the p-type well region 54 sandwiched by the n-type source region 56 and n-type well region 52, and a stripe-form n-type drain region 55 disposed distanced from the p-type well region 54. A LOCOS 60 is disposed between the p-type well region 54 and n-type drain region 55. The semiconductor device 500 includes a p-type well region 30 disposed so as to enclose the p-type well region 54 group, and a ring-form p+ region 31 disposed in a surface layer of the p-type well region 30. A guard ring 32 is configured of the p-type well region 30 and p+ region 31.
Also, a parasitic diode 65 is configured of the p-type well region 54 and n-type well region 52 configuring the cell of the output stage MOSFET 501. The parasitic diode 65 forms a surge protection element 66.
An n-type well region 21 forming an integrated circuit 102 is formed distanced from the n-type well region 52 in a surface layer of the p-type semiconductor substrate 51. The n-type well region 21 is in contact with the p-type well region 30, and a p+ region 33 is disposed in the p-type well region 30 between the n-type well region 52 and n-type well region 21.
A distance L4 of the n-type well region 52 between the p-type well region 30 of the guard ring 32 and the p-type well region 54 configuring a cell 54a of the output stage MOSFET 501 is longer than a distance L3 of the n-type well region 52 (drift region) between the p-type well region 54 and n-type drain region 55 of the output stage MOSFET 501. This is so that avalanche will occur in a p-n junction D between the p-type well region 54 configuring the cell 54a of the output stage MOSFET 501 and the n-type well region 52 before occurring in a p-n junction C between the p-type well region 30 and n-type well region 52 on the guard ring 32 side when a surge such as an ESD is applied to the n-type drain region 55. The semiconductor device 500 is protected from the surge by avalanche occurring simultaneously in the p-n junctions D between the p-type well regions 54 configuring the cells and the n-type well region 52. The cell 54a configuring an active region 68 (the device region excluding the guard ring 32) of the output stage MOSFET 501 ranges from the center of the p-type contact region 57 to the center of the n-type drain region 55, is configured of the n-type source region 56, p-type well region 54, n-type drift region (n-well region 52), and n-type drain region 55, and a plurality thereof are disposed.
In FIG. 9, ground wiring 64, gate wiring 61a, source electrode wiring 63, and drain electrode wiring 62 are formed of aluminum wiring, and the aluminum wirings are disposed on an unshown interlayer insulating film on the n-type well region 52 or LOCOS 60. Each electrode wiring and semiconductor region, and the gate electrode 61 and gate wiring 61a, are connected via a contact hole formed in the interlayer insulating film.
FIG. 10 is a current (Id)-voltage (Vd) characteristic diagram for the output stage MOSFET 501. Id is the drain current of the output stage MOSFET 501, while Vd is the drain voltage of the output stage MOSFET 501. Id also indicates a surge current flowing through the output stage MOSFET 501 and the collector current of the parasitic diode 65. Also, Vd also indicates a surge voltage applied to the output stage MOSFET 501 and a surge voltage applied to the parasitic diode 65.
The drain current (Id) begins to flow at the point at which the drain voltage (Vd) of the output stage MOSFET 501 reaches an avalanche voltage, and when the drain current increases, the drain voltage also increases. ΔId/ΔVd is the operating resistance of the surge protection element 66, while the drain voltage when the surge current flows is the operating voltage of the surge protection element 66. The dotted line in FIG. 10 indicates a variation in current-voltage characteristics caused by manufacturing variation.
Among surges, an ESD surge can be thought of as a high energy pulse generated when an electrically-charged person or thing touches an integrated circuit. The following patent documents have been disclosed as methods of protecting a MOSFET configuring an integrated circuit from the ESD.
In Japanese patent publication no. JP-A-2002-94063, a protective thyristor is formed on the same chip in order to protect a MOSFET configuring an integrated circuit from an ESD. It is described that, by the protective thyristor formed in a separate place on the same chip being caused to break down before the MOSFET configuring the integrated circuit enters an avalanche condition when an ESD surge is applied, the MOSFET is protected.
Also, in Japanese patent publication no. JP-A-2005-183499, the drain-to-source distance of a MOSFET configuring an integrated circuit is partially shorter, and this portion forms a protective thyristor portion. It is described that, by the breakdown voltage of the protective thyristor portion being lower than the breakdown voltage of the MOSFET portion, and the protective thyristor portion being turned on when an ESD surge is applied, thereby creating a state of low impedance, the MOSFET is protected.
Also, in Japanese patent publication no. JP-A-2007-294614, it is described that a p-type region is formed sandwiching an n-type drain so as to oppose an n-type source, and an n-type region is formed on the outer side of the p-type region so as to be in contact with a p-type isolation region, thereby forming a p-n-p transistor.
Also, in Japanese patent publication no. JP-A-2001-320047, it is described that a thyristor structure is obtained by a p-type anode layer being formed adjacent to an n-type drain and in contact with a drain electrode.
However, the semiconductor device 500 of FIGS. 7 to 9 is such that, as the surge protection element 66 is the parasitic diode 65, which is formed in each cell 54a, variation occurs in the avalanche voltage in each cell 54a when there is manufacturing variation. When a surge such as an ESD is applied, the surge current concentrates in a cell 54a with a low avalanche voltage rather than all the cells 54a operating in unison, snap-back occurs over a small area in a parasitic transistor 70, as shown in FIG. 10, and the parasitic transistor 70 is destroyed.
Also, as the area occupied by the active region 68 in which the cells 54a are formed is large in comparison with that of the guard ring 32, there is a tendency for the in-plane variation (i.e., manufacturing variation) of the diffusion concentration and diffusion depth to increase in the active region 68. When there is manufacturing variation in this way, variation occurs in the operating resistance and operating voltage of the surge protection element 66, the surge current concentrates in the parasitic diode 65, which has low operating resistance and operating voltage, and the surge protection function depreciates. That is, the conventional semiconductor device 500 is such that the evenness of the surge protection function is liable to be affected by manufacturing variation.
Further, the device described in Japanese patent publication no. JP-A-2002-94063 is such that, as the protective thyristor is formed in a separate place on the same chip, the chip area increases. Also, as the protective thyristor is formed in a separate region, it may happen that the breakdown voltages of the protective thyristor and the MOSFET configuring the integrated circuit are reversed due to variations in the manufacturing process, and protection of the MOSFET becomes difficult.
Also, the device described in Japanese patent publication no. JP-A-2005-183499 is such that there are problems in that, as the drift length differs between the MOSFET portion and thyristor portion, the current flows unevenly, and furthermore, as the width W of the MOSFET portion is small, the on-state voltage of the MOSFET increases.
Still further, in Japanese patent publication no. JP-A-2007-294614, it is described that the p-n-p transistor, which is an ESD protection element, is formed in contact with the p-type isolation region, but there is no description of forming a parasitic bipolar transistor on a guard ring configuring a MOS transistor.
Also, the device described in Japanese patent publication no. JP-A-2001-320047 is such that a protective thyristor is formed in each cell, because of which, when there is manufacturing variation among the cells, surge current caused by an ESD surge concentrates in a specific cell as an effect of the variation, and destruction is likely.
Moreover, in Japanese patent publication nos. JP-A-2002-94063, JP-A-2005-183499, JP-A-2007-294614, and JP-A-2001-320047, there is no description of forming the ESD protection element collectively in a place in which the guard ring of the output stage MOSFET is formed. Thus, as is described above, there are needs in the art for improved semiconductor devices including surge protection elements.